Leads of a no-lead type package of a semiconductor device

ABSTRACT

The present invention relates to leads of a No-Lead type package which includes a chip having an active surface and a rear surface opposite the active surface. The active surface has a plurality of connection points with a plurality of leads arranged around the perimeter of the chip and a first and a second surface orthogonal to said first surface. A plurality of connection wires connect electrically the bonding pads of the chip to the first surface of the leads respectively. The package also includes a welding compound suitable for encapsulating the chip, the first surface of the leads and the bonding pads. The leads possess at least one hole in the second surface of the leads.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention refers to the leads of a No-Lead typepackage of a semi-conductor device, in particular but not exclusively tothe leads of a Quad Flat No Lead type package of a semiconductor device.

[0003] 2. Background of the Invention

[0004] Pursuing the evolution of integrated circuits, the manufacturingprocess of an integrated circuit has reached such levels of integrationthat there is the need to use package structures capable of meeting theincreasingly insistent requests for reduction in cost, weight, section,and dimensions with the same reliability and usability.

[0005] These needs have been partially resolved through the introductionof a family of package commonly known as Chip Scale Package (CSP), whosecharacteristics include the reduction of dimension and weight, an easierassembly process, an increase in performance and a general reduction inproduction costs.

[0006] The reduction of dimensions and weight are probably the mostimportant factors among these characteristics, for use of the CSPtechnology.

[0007] In particular CSP technology can be divided into two largepackage types: 1) the so-called Grid Arrays; 2) the so-called Quad FlatLeads.

[0008] A transversal section of a known package of the Quad Flat Leads(QFL) type is shown in FIG. 1.

[0009] The structure 1 of the QFL package, having a die pad 2 surroundedby a plurality of leads 3, can be seen in said FIG. 1. The presence of achip 4 that has an active surface 5 and a rear surface 6 can also benoted. Chip 4 has its rear surface 6 connected to the die pad 1, whilethe active surface 5 provides for a plurality of bonding pads 7 formaking the external connections of the chip 4 itself.

[0010] The bonding pads 7 are electrically connected to the leads 3 bymeans of bonding wires 8.

[0011] In addition a molding compound 9 normally encapsulates the wholechip 4, the die pad 1, the bonding wires 8 and a portion of the leads 3.

[0012] The QFL typology, just illustrated, in turn provides for acategory without the leads themselves, that is the Quad Flat No-Lead oLeadless (QFN) typology.

[0013] A package like this carries to the extreme the concepts ofminiaturization, as it presents a reduced package footprint, a thinprofile and reduced weight.

[0014] Consequently, the manufacturers of video cameras, cellulartelephones and laptops heavily rely on the use of QFN in theirconsumption products.

[0015] A section view of a Quad Flat No-Lead package of a semiconductorin accordance with the known art is shown in FIG. 2.

[0016] A plan view of the rear side corresponding to FIG. 2 is shown inFIG. 3.

[0017] As shown in FIGS. 2 and 3 this type of package 23 includes a diepad 10 that has a plurality 11 of leads surrounding the die pad 10itself. The presence of a chip 12 that has an active surface 13 and arear surface 14 can also be seen. On the active surface 13, there are aplurality of bonding pads 15 suited to enabling the external connection.The rear surface 14 of the chip 12 is connected to the upper surface 16of the die pad 10 by means of an adhesive layer 17, while the bondingpads 15 are electrically connected to the upper surface 18 of the leads11 respectively by means of a bonding wire 19.

[0018] In addition, the die pad 10 is usually connected to ground bymeans of a bonding wire 22 so as to increase the electrical performancethrough a reduction of the interferences.

[0019] A molding compound 60 encapsulates the whole chip 12, the bondingwires 19, and the upper surface 18 of the leads 11 while it exposes thelower surface 20 and the side surface 21 of the leads 11 for theexternal connections.

[0020] In fact the lower surface 20 of the leads 11 is successivelywelded to a PCB (Printed Circuit Board), as shown in FIG. 4, throughtechnical means that are well known to a technician of the sector.

[0021] A micro-section 24 between a lead 11 and a bonding pad 25 of aPCB 26 is illustrated in said FIG. 4. There is a welding paste 27between the lead 11 and the bonding pad 25 of the PCB 26.

[0022] The main problem of the QFN packages is caused by thenonalignment (mismatch) between the leads and the PCB, which is createdduring the turn on/turn off cycles of the device in the interval of theoperative temperatures provided for, because of the different thermalexpansion of the materials involved.

[0023] This brings high mechanical stress in the welding points betweenthe leads and the PCB, as shown successively in FIG. 6.

[0024] This problem is accentuated because of the intrinsic structure ofthe QFN package, due that is to the shape of the contact pad and thedimensions of the pad, as the welding joint between the package QFN andthe PCB is extremely small.

[0025] In fact, given the structure of the leads 11 of the QFN package,it is technically complex and economically unfavorable to increase thelower contact surface 20 of the leads 11 with the PCB, as this wouldlead to an increase in the footprint of the QFN package and thereforethe occupation of a greater area.

[0026] The Applicant has carried out various turn on/off simulations ofthe chip 12, verifying the behavior of the welding points between QFNpackage and PCB, noting in particular that there are various problems,among which: 1) electrical failures; and 2) high torsion stress in thewelding with consequent early mechanical breakages of the welding point.

[0027] A graph is represented in FIG. 5, having the number of cycles onthe x coordinate and on the y coordinate the percentage of failures, oftwo devices, having different physical dimensions and representedrespectively with a circle (device with greater dimensions) and atriangle (device with lower dimensions), from which it can be deductedthat several cycles of turn off/on are enough (around a few hundred), inan interval of operative temperatures of between −40° C. and +150° C.,to cause electrical failures of the welding joint.

[0028] In addition this phenomenon is overemphasized when the dimensionof the package is increased.

[0029] The Applicant has also verified that breakages occur in thewelding joints, when said devices are submitted to the same test cycles,that depend mainly on the dimension of the lead, noting that the smallerthe lead is, sooner occur the breakages in contrast with what happensfor electrical failures.

[0030] A micro-section 28 between a lead 11 and a pad 25 of a PCB isshown in FIG. 6. From this micro-section 28 a mismatch between lead 11and pad 25 can be seen, with lack of welding material 27. This leadsboth to a deterioration of the electrical performance of the joint andto lower mechanical reliability of the joint.

[0031] Other problems that afflict the QFN packages can arise during theprocess of cutting the QFN package itself from the lead frame, a processknown as a “singulation process”.

[0032] In fact, during this operation, as the leads 11 of the QFNpackage are cut mechanically by means of cutting tools and as theseleads 11 are emerged in the plastic package 60, there is a possibilitythat when the cut is made a delaminating is created on the side surfaces21 of the leads 11.

[0033] This means that the bonding wires 19 welded on the upper surface18 of said leads 11 can be stressed, making the joint mechanically weak.

[0034] Unfortunately the common QFN packages show considerabledelaminations between the end of the leads and the welding compound,with the obvious repercussions on the level of reliability of thedevice.

[0035] This inconvenience cannot be attenuated, not even with the use ofrefined and very expensive molding compounds.

[0036] Another inconvenience is found in the fact that following theoperation of cutting the QFN package from the lead frame, the sidesurface 21 of the lead 11 is exposed to the ambient atmosphere.

[0037] As the lead 11 is generally made with a material such as copper,this oxidizes rapidly causing a drop in the electrical performance.

[0038] Another inconvenience that affects the QFN packages occurs whenthe QFN package itself is welded onto PCB.

[0039] In fact, a lead 11 of the QFN package only offers the lowersurface 20 to carry out the operation of welding to the PCB.

[0040] This entails a welding joint having a reduced contact surface,thus making it weaker and thus more easily subjected to mechanicalbreakages.

[0041] In addition the material making up the leads 11 cannot be weldedto the PCB until after an electroplating operation.

[0042] From what has been shown up to now, the doubtless advantagesoffered by the Quad Flat No Lead packages appear evident, but the numberand type of technical problems that have to be dealt with in producingsuch packages are also evident.

SUMMARY OF THE INVENTION

[0043] In view of the state of the technique described, the object ofthe present invention is to reduce the mechanical stress on the leads ofthe QFN package during the cutting process.

[0044] Another object of the present invention is to increase thewelding surface between the leads of the QFN package and the PCB.

[0045] In accordance with the present invention, this object is reachedby means of leads of a No-Lead type package of a semiconductor device,said No-Lead type package comprising: a chip, having an active surfaceand a rear surface opposite said active surface, said active surfacehaving a plurality of connection points; a plurality of leads, arrangedaround the perimeter of said processor and having a first and a secondsurface orthogonal to said first surface; a plurality of connectionwires that electrically connect said bonding pads of said processor tosaid first surface of said leads respectively; a welding compound,suitable for encapsulating said chip, said first surface of said leadsand said bonding wires so as to form said package; as said leads arecharacterized in that each one of them possesses at least one hole insaid second surface of said leads.

[0046] Thanks to the present invention the surface of the lead submittedto the cutting process can be minimized, so as to reduce mechanicalstress of the welding joint between lead and PCB.

[0047] In addition thanks to the present invention the weldable surfaceof the lead can be increased, so as to diminish the delaminating and theoxidation.

[0048] In addition the present invention favors the separation of theQFN package from the lead frame.

BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The characteristics and the advantages of the present inventionwill appear evident from the following detailed description of someembodiments thereof, illustrated as non-limiting examples in theenclosed drawings, in which:

[0050]FIG. 1 shows a transversal section of a quad flat leads typepackage, according to the known technique;

[0051]FIG. 2 shows a transversal section of a quad flat leads typepackage, according to the known technique;

[0052]FIG. 3 shows a plan view of the rear side corresponding to FIG. 2;

[0053]FIG. 4 shows a micro-section between a lead and the PCB, accordingto the known technique;

[0054]FIG. 5 shows a graph indicating the results of varioussimulations;

[0055]FIG. 6 shows another micro-section in the case of a breakagebetween a lead and the PCB;

[0056]FIG. 7 shows a plan view of the rear side of an embodiment of theleads in accordance with the present invention;

[0057]FIG. 8 shows in detail a detail of FIG. 7;

[0058]FIG. 8a shows a comparison between a lead in accordance with thepresent invention and a known lead;

[0059]FIG. 9 shows a further embodiment of the present invention;

[0060]FIG. 10 shows a three-dimensional view of the embodiment of FIG.9;

[0061]FIG. 11 shows another embodiment of the present invention;

[0062]FIGS. 12 and 12a show another embodiment of the present invention;

[0063]FIGS. 13 and 13a show a successive embodiment of the presentinvention; and

[0064]FIG. 14 shows a further embodiment of the present invention.

DETAILED DESCRIPTION

[0065] A plan view of the rear side of an embodiment of the presentinvention is shown in FIG. 7. Said FIG. 7 shows a plurality of leads 71that surround die pad 70 of a package 61. These leads 71 have aparticular missile shape as can be seen in FIG. 8.

[0066] In fact, as shown in detail in FIG. 8, said leads 71 have arectangular shape for the external portion 62 of the package 61, whilefor the internal portion 63 of the package 61 they have a shape thatresembles a missile.

[0067] In this manner a contact surface of over about 20% is obtained,in comparison with traditional leads 11 as shown in FIG. 8a, with theobvious advantages that derive.

[0068] As said FIG. 8a shows, the innovative lead 71 is obtained thanksto a chemical etching process by means of which lead 71 itself can beetched for a depth equal to the half of the material constituting thelead 71, commonly known as half etching process.

[0069] In this manner a type of step 80 is obtained thanks to which themolding compound 60 finds a more efficient hold.

[0070] In other words the lead 71 for the portion 63 undergoes achemical etching operation by means of a specially made process mask,thanks to which a low relief zone 80 is created which acts as anchoragebetween the molding compound 60 and the lead 71 itself.

[0071] In addition as can be deducted from said FIG. 8, the surfaceportion 62 of the lead 71, outside the package 61, has a lineardimension 76 which is greater than the linear dimension 77 of theinternal surface portion 63.

[0072] A further embodiment of the present invention is shown in FIG. 9.

[0073] According to what is illustrated in said FIG. 9, a plurality ofleads 71 can be seen which have respectively a hole 32, a first medianline 33 of said leads 71 and a second line 34, representing the cuttingline (dam bar) between the QFN package and the lead frame 50.

[0074] Said hole 32, in this particular embodiment, is a through holeand has a circular section with its center C at the point at which saidmedian line 33 crosses over said cutting line 34.

[0075] A three-dimensional view of a lead 71 after the operation ofcutting the QFN package from the lead frame 50 has been carried out isshown in FIG. 10.

[0076] As can be seen in said FIG. 10, the lead 71 presents an uppersurface 35, a side surface 36 and a lower surface 38.

[0077] It is to be noted that the upper surface 35 is the surface thatis welded to the PCB, after the electro-plating operation, while thelower surface 38 is the surface that possesses the bonding pad suitablefor connecting the chip 12 by means of the bonding wire 19 towards theoutside.

[0078] The side surface 36 presents a cylindrically-shaped etching 39,result of the operation of cutting the QFN package from the lead frame50 thanks to the presences of said through hole 32.

[0079] As previously said one of the problems of the leads 11 belongingto traditional QFN packages is due to the fact that they have only onesurface that can be welded to the PCB.

[0080] With the present invention, the lead frame 50, after post moldcuring, undergoes a plating operation. In this manner also the throughhole 32 is plated and therefore also the side surface 36, specificallyin the cylindrically-shaped etching zone 39, can be welded to a PCB (notshown in FIGS. 9 and 10).

[0081] Therefore, following the welding operation, the leads 71 of theQFN package are electro-plated with a tin-lead alloy, as with the leadframe 50.

[0082] In this manner the side surface 36 becomes weldable increasingconsiderably the surface of the leads 71 welded to the PCB, as inaddition to the usual lower surface 35 there is also the side surface36.

[0083] Nevertheless, the invention does not increase the footprint ofthe QFN package.

[0084] The remaining perimetric zone of the side surface 36 cannot bewelded, because the electro-plating operation does not concern them, asthey are encapsulated by the resin 60.

[0085] Obviously, the position and the geometrical shape of the throughhole 32 can be different as shown in FIGS. 9 and 10.

[0086] In fact the Applicant has found it just as effective to carry outholes 32 positioned on the perimetric zones 37 of the leads 71, as shownin FIG. 11.

[0087] In said FIG. 11 it can be seen that the lead 71 possesses a pairof holes 32 in the perimetric zones 37, entailing a doublecylindrically-shaped etching 52.

[0088] In this case the electro-plating operation concerns the uppersurface 35 and the cylindrically-shaped etchings 52.

[0089] In addition the Applicant has found just as effective to carryout holes 32 with elliptical or quadrangular shapes, the latter withpointed or smoothed corners, as shown in FIGS. 12 and 12a.

[0090] In said FIGS. 12 and 12a it can be noted that the lead 71possesses a through hole 32 with quadrangular section in the sidesurface 36, originating an etching 56 with a parallelepiped shape.

[0091] In this case the electro-plating operation concerns the uppersurface 35 and the etching 56 with a parallelepiped shape.

[0092] In addition, the Applicant has made leads 71 with two or moreholes 32 with a circular section, elliptical or quadrangular on the sidesurface 36 or in the perimetric zones 37, as shown in FIGS. 13 and 13a.

[0093] In said FIGS. 13 and 13a it can be seen that the holes 32 areplaced at the end of the side surface 36, giving rise to a doublecylindrically-shaped etching 58.

[0094] In this case the electro-plating operation concerns the uppersurface 35 and the double cylindrically-shaped etching 58.

[0095] In conclusion, the Applicant made leads 71 with one or more blindholes 32, with a circular, elliptical or quadrangular section, on theside surface 36, said blind holes 32 having a depth which depends on thedimensions of the lead 71 itself, as shown in FIG. 14.

[0096] In said FIG. 14 it can be seen that the blind hole 32, has adepth D which exceeds half the height H of the lead 71.

[0097] It is also to be noted that in the embodiments illustrated inFIGS. 9, 10, 12, 12 a, and 14, the hole 32, whatever section it has, hasbeen represented as having its center C on the meeting point betweensaid median line 33 and said cuffing line 34, but, just as valid theembodiments in accordance with which the center C of the hole 32 isplaced in any point of the external surface portion 62 of the lead 71,as long as said sections cross over with said cutting line 34.

1. Leads for a “No-Lead” type package of a semiconductor device, said No-Lead type package comprising: a chip having an active surface and a rear surface opposite to said active surface, said active surface having a plurality of connection points; a plurality of leads arranged around the perimeter of said processor and having a first and a second surface orthogonal to said first surface; a plurality of connection wires which connect electrically said bonding pads of said chip to said first surface of said leads respectively; and a welding compound suitable for encapsulating said processor, said first surface of said leads and said bonding wires so as to form said package; each of said leads possessing at least one hole in said second surface of said leads.
 2. Leads for a “No-Lead” type package of a semiconductor device according to claim 1, wherein said at least one hole is a through hole.
 3. Leads for a “No-Lead” type package of a semiconductor device according to claim 1, wherein said at least one hole is blind, whose depth (D) depends on the dimensions of said lead.
 4. Leads for a “No-Lead” type package of a semiconductor device according to claim 2, wherein said at least one hole is a hole with a circular section.
 5. Leads for a “No-Lead” type package of a semiconductor device according to claim 2, wherein said at least one hole is a hole with an elliptical section.
 6. Leads for a “No-Lead” type package of a semiconductor device according to claim 2, wherein said at least one hole is a hole with a quadrangular section, with pointed or smooth corners.
 7. Leads for a “No-Lead” type package of a semiconductor device according to claim 1, wherein said leads have a first dimension external to said package and a second dimension internal to said package, said first dimension being greater than said second dimension.
 8. Leads for a “No-Lead” package of a semiconductor device according to claim 1, wherein said leads have a first surface portion external to said package having a rectangular shape, and a second surface which is a continuation of said first surface and internal to said package, having a missile shape. 